The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having spare memory cells for replacement of defective memory cells which are then programmably accessible.
Modem microprocessors and many Application Specific Integrated Circuits (ASICs) often incorporate large amounts of embedded memory. This memory is typically Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). These Random Access Memories (RAMs) constitute the majority of transistors contained on a chip and can occupy the largest portion of the surface area of a chip, i.e., chip xe2x80x9creal estate.xe2x80x9d Availability and usability of these RAMs becomes a priority to semiconductor manufacturers. Typically semiconductor manufacturers incorporate a test and a repair scheme which tests RAM cells within the chip and replaces defective RAM cells with spare cells included for that purpose. Typically, columns and/or rows of RAM cells are replaced rather than individual RAM cells. Row substitution may be performed by appropriate changes to the address decoder while column substitution may be performed by MUX selection of appropriate bit lines.
Traditionally, semiconductor manufacturers have used bit maps to determine which RAM columns and/or RAM rows need to be replaced with redundant RAM columns or RAM rows. Identification of defective memory cells is a particular problem when embedded on a microprocessor or ASIC device, since external or off-chip access for testing is limited by the number of pins available. Thus, semiconductor manufacturers have incorporated Built In Self Tests (BISTs) and Built In Self Repair (BISRs) to test and replace RAM cells. Special purpose built-in test hardware is described in detail in the commonly assigned and co-pending U.S. patent application entitled, xe2x80x9cA Flexible And Programmable BIST Engine for On-Chip Memory Array Testing and characterization,xe2x80x9d Ser. No. 09/183,536, filed on Oct. 30, 1998 and hereby incorporated, in its entirety, by reference.
Typically RAM cells are tested for a number of faults which can be classified into two categories, simple faults and linked faults. Simple faults are those which occur independent of other faults but may induce failures in other cells. Linked faults are when two or more simple faults are acting on a single cell (i.e. multiple faults influencing each other). Simple faults can be further divided into Address Decoder Faults (ADFs) and Memory Cell Array Faults (MCAFs). ADFs are only present in the address decoder and result in the unavailability of a cell, the lack of an address to access a cell, an address accessing multiple cells, or a specific cell being accessible with multiple addresses.
MCAFs can be further broken down into single cell faults and faults which occur between memory cells. Single cell faults include Stuck At Faults (SAFs), Stuck Open Faults (SOFs), Transition Faults (TFs), and Data Retention Faults (DRFs). SAF means a specific cell is either xe2x80x9cstuckxe2x80x9d at zero or xe2x80x9cstuckxe2x80x9d at one regardless of the data attempted to be written into the cell. SOF indicates that a memory cell cannot be accessed because of an open line. A TF occurs when a memory cell cannot make a transition from zero to one, or from one to zero. And finally, a DRF occurs when a cell is unable to retain a particular logic value or state for a requisite period of time.
Coupling faults involve two cells. A first cell, the coupling cell, which is the source of the fault, and the second cell, the coupled cell, which is the cell that experiences the fault. These coupling faults can occur either when a transition occurs in the coupling cell or when a specific value is stored in the coupling cell. Transitions in a coupling cell can cause the coupled cell to change from a zero to a one, or vice versa, or can cause a zero or a one to be stored within the coupled cell. Additionally, certain values in coupling cells may bleed through to a coupled cell regardless of the value which should be stored in the coupled cell.
Tests which are applied in parallel to a plurality or group of memory cells, or march tests, consist of a sequence of elements, or xe2x80x9cmarch elements,xe2x80x9d in which a sequence of operations are defined and corresponding data signals are applied to various memory cells, typically one row or column at a time. The overall memory can be divided into memory groups and these tests can occur in parallel across memory groups. The address order determines the order in which the march test is applied to various address locations within a memory group. A march test may contain the following sequence: write zero, read zero, write one, read one, write zero, read zero. This march test would ensure that a zero could be stored in, and read from, a memory cell, that a one can be stored in, and read from, a memory cell, and that the memory cell can transition from a zero to a one, and from one to zero. These march tests are performed on the memory cells during BIST.
Once faulty memory cells have been identified, BISR is used to replace the faulty memory cells with spare memory cells. This typically occurs a column or row at a time or using multiple spare columns or rows to replace a continuous group of columns or rows (e.g., an address space spanning several rows or columns). Semiconductor manufacturers also combine BIST and BISR in accordance with their testing philosophy. BIST could be completed before the BISR has been implemented and not repeated after array reconfiguration in which faulty rows or columns are replaced with spare ones. Thus, if BIST is completed before BISR is performed, the replacement columns and rows are not typically tested during BIST and columns and rows of cells would be included in the operational memory array which have not successfully passed BIST.
Alternatively, and more preferably, BIST and BISR can occur alternatively to ensure that each of the memory cells contained in the final (operational) memory array configuration have been thoroughly tested. For instance, one march test may occur during the first pass of BIST and be used to identify faulty memory cells. Once these faulty memory cells have been identified, a first pass of BISR can be used to replace the rows and/or columns of memory which contain these faulty memory cells. Once the first pass of BISR has been completed, the second pass of BIST can be performed which repeats the first BIST pass or which includes additional march tests to ensure that the replacement rows and/or columns, as configured, are operating properly. A second pass of BISR would be performed at the conclusion of the second pass of BIST to replace any newly identified or remaining faulty rows and/or columns. In addition, other march tests can be performed which test for coupling problems between memory cells in the reconfigured array. A BIST, which identifies memory cells with faults, is always followed by BISR, or the memory array is unrepairable and discarded.
Once a row of memory containing a non-operational cell has been identified, its address is typically stored and mapped to a redundant row. This mapping may occur after each row containing a non-operational cell has been identified, or alternatively, testing may be suspended while the row containing the non-operational cell is mapped to a redundant row. Once the mapping is completed, testing of the remaining rows is resumed. For memory addresses which cannot be accessed or stored in a single clock cycle a pipeline may be implemented to allow the access or storage to occur over numerous clock cycles.
A description of memory testing and the use of redundant memory elements is described in detail in the commonly assigned U.S. Pat. No. 6,141,779 issued Oct. 31, 2000, and co-pending U.S. patent application entitled, xe2x80x9cSystem and Method for Providing RAM Redundancy in the Field,xe2x80x9d Ser. No. 09/544,516 filed on Apr. 6, 2000, both herein incorporated, in their entireties, by reference. Also U.S. Pat. No. 5,255,227 issued Oct. 19, 1993 to Haeftele, U.S. Pat. No. 5,848,077 issued Dec. 8, 1998 to Kamae et al. and U.S. Pat. No. 6,000,047 issued Dec. 7, 1999 to Kamae et al., each commonly assigned to the assignee of this patent describe similar correction methods and are herein incorporated, in their entirety, by reference.
While BIST and BISR provide enhanced testing facilities and rehabilitation of faulty devices, the additional test and repair circuitry and time used limits incorporation of these tools into the already cramped chip real estate. Accordingly, a need exists for a systematic method and approach to test the memory cells contained within a memory array that will minimize the amount of time spent in BIST and BISR while maximizing the identification of faulty memory cells. A need further exists for the efficient use of redundant memory columns and redundant memory rows in the replacement of faulty memory cells. A further need exists for the identification and replacement of faulty memory cells while minimizing the hardware associated with the BIST, BISR, and surface area of the chip dedicated to BIST and BISR.
The identified needs, additional advantageous features and technical advantages are achieved by a system and method of eliminating faulty memory cells from a memory array, the method comprising the steps of detering if cells in each column of the memory array are operational (i.e., are not faulty), replacing columns of the memory array which include more than a predetermined number (e.g. one) of non-operational cells with spare columns and, once these columns are replaced, using one or multiple spare rows to replace any row (and, in the case of multiple spares, adjacent rows) which contains one or more non-operational cells. As used herein eliminating means electrically bypassing or switching in substitute cells without physically removing the non-operational cells. The determination of operational versus non-operational cells may include the testing of each memory cell within the memory array and the number of defective cells within a column may be counted to determine when column replacement should be used because a threshold value has been reached or surpassed or based on the actual number of failed memory cells within the column.
The test used to determine whether the memory cell is operational or not may comprise the steps of generating at least one memory address, writing data to the generated memory address, reading data from the memory address, and comparing the data read from the memory address with the data which was written to the memory address. The configuring of columns of the memory array may be performed by bit line multiplexers which are used to shift-in a replacement column (or group of replacement columns) of memory cells into the array. The configuring of rows of the memory array may include translating or alternately decoding a row address signal which designates which rows are included in the memory array and which rows are excluded from the memory array. One or more spare rows may be selected to replace rows containing non-operational cells with the rows being replaced. Additional testing may be performed after the columns containing more than one non-operational cell are replaced with spare columns. Built-in self test may be used to perform the testing to determine non-operational cells and built-in self repair may replace the columns and the rows with spare columns and rows respectively.
Another embodiment of the invention includes a system for eliminating faulty memory cells from a memory array, the system comprising a memory cell tester which determines non-operational cells, a column selector or xe2x80x9creconfigurerxe2x80x9d which replaces columns having more than one (or some other predetermined value of) non-operational cells with a spare column, and a row reconfigurer which replaces any row containing non-operational memory cells remaining after column replacements have been made with spare rows. The memory cell tester may count the number of non-operational cells in each of the columns and use that number to determine the columns which should be replaced by spare columns, or may use a threshold value based circuit (e.g., saturation counter) that ensures columns with a number of non-operational cells which equal or exceed the threshold be replaced with spare columns. The memory cell tester may include a memory cell data write circuit or xe2x80x9cwriterxe2x80x9d which writes values into the memory cell, a memory cell data read circuit or xe2x80x9creaderxe2x80x9d which reads values from the memory cell, a first register to store the value written into the memory cell and a comparator which compares the value read from the memory cell to the value stored in the first register. A second register may be used to record a count, representing the results from the comparator. The column reconfigurer may comprise a bit line multiplexer used to shift a replacement column of memory cells into the memory array. The row reconfigurer may comprise a row address signal which is used to select one or more spare rows of memory cells to replace rows of memory cells which contain non-operational cells.
Another embodiment of the invention reverses the preferred column first, row second ordering and comprises a method of eliminating faulty memory cells from a memory array which xe2x80x9clooks atxe2x80x9d or tests and performs reconfiguration of the rows first and then the columns. In this embodiment, a determination is made of the number of non-operational cells in each of the rows of the memory array, rows having more than a set predetermined or dynamically adjusted number of non-operational faults being replaced with spare rows. Once those non-operational memory cells are effectively xe2x80x9cremovedxe2x80x9d from the memory array, the columns containing non-operational memory cells are identified and spare columns are used to eliminate the columns containing the non-operational cells from being included in the memory array. The determination as to whether a cell is operational or non-operational includes a step of testing the memory cells of the memory array to determine defective cells and counting the defective cells in each of the rows. The count itself can be used to determine the rows which should be replaced with spare rows or a threshold and corresponding boolean value may be used. The memory cell testing comprises the steps of generating at least one memory address, writing data to the memory address, reading data from the memory address, and ensuring the correct data was read from the memory address. A register may be used in this testing. Configuring the rows of the memory array may include a step activating an alternate word line to shift in a replacement row of memory cells into the array or otherwise access the replacement row or rows.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.